Besides the Edward Snowden revelations, the unending list of high-profile hacks in the past few years reduced the confidence of the people on computer applications. This directs computer architects that traditional computing is neither safe nor secure.
At the same time, key initiatives such as cloud computing and the IoT (Internet of Things) are gaining popularity but require a high performance and secure processing system that can solve their problems. The UCERD Processor-based System Research Group (PSRG) intend to develop high performance and secure processing system architecture.
The Processor-based System targets different instruction set architecture, with a specific focus on performance, reliability and security.
The on-chip computing power of microprocessor technology and processor memory speed gap also affects the performance of a system. In parallel the emergence of multi-core chips adds, however, an extra dimension to this problem, concurrent and competing access to the specific resource. The PSRG tries to solve these problems by proposed novel hardware architecture, modification and programming techniques.
The PSRG works on following Multi Processors problems:
Develop High Performance Processor Architecture using RISC-V ISA.
Access a shared memory location concurrently without a major impact on performance.
Prioritize and administer parallel and competing requests to different locations in the memory.
Provide guarantee integrity and consistency over time of data logically belonging to different cores; in general.
Exploit a specific resource (memory bandwidth and on-chip memory) that just got a lot scarcer.
The PSRG are currently working on:
Seucre Processor based System using RISC-V ISA
FPGA based Systems
Vector Processor Architectures
Memory System for High Performance Systems
[1] Memory Resources Aware Run-Time Automated Scheduling Policy for Multi-core Systems, Tassadaq Hussain. ScienceDirect Microprocessors and Microsystems 2017. ISSN: 0141-9331 IF: 1.025
[2] Formation of pn-junction with stable n-doping in graphene field effect transistors using e-beam irradiation. Muhammad Zahir Iqbal, Nadia Anwar, Salma Siddique, Muhammad Waqas Iqbal, Tassadaq Hussain. Journal of Optical Materials 2017, ISSN: 0925-3467 IF: 2.238
[3] A Novel Hardware Support for Heterogeneous Multi-core Memory System : Tassadaq Hussain, ScienceDirect Journal of Parallel and Distributed Computing 2016, ISSN: 0743-7315. IF: 1.930
[4] PMSS: A Programmable Memory System and Scheduler for Regular Memory Patterns: Tassadaq Hussain, Eduard Ayguade and Amna Haider. ScienceDirect Journal of Parallel and Distributed Computing 2014. ISSN: 0743-7315 IF:1.930
[5] AMC: Advanced Multi-core Controller: Tassadaq Hussain, Amna Haider, Shakaib Arsalan and Eduard Ayguade. ScienceDirect Journal of Parallel Computing 2014. ISSN: 0167-8191 IF: 1.511
[6] Memory Controller for Vector Processor: Tassadaq Hussain, Springer Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 2016. ISSN: 1939-8018 IF: 0.893
[7] HMMC: A Memory Controller for Heterogeneous Multi-core System, Tassadaq Hussain. ScienceDirect Microprocessors and Microsystems 2015. ISSN: 0141-9331 IF: 1.025
